Semiconductor device fabrication is a process used to create integrated circuits that are present in many electrical and electronic devices. It is a multiple-step sequence of photolithographic, mechanical, and chemical processing steps during which electronic circuits are gradually created on a wafer made of semiconducting material. For example, during semiconductor device fabrication, numerous discrete circuit components, including transistors, resistors, capacitors, inductors, and diodes may be formed on a single semiconductor die.
In many applications, semiconductor device fabrication may employ shallow trench isolation (STI). STI is an integrated circuit feature which may prevent electrical current leakage between adjacent semiconductor components, especially for relatively fine feature sizes (e.g., less than 250 nm). STI is often created early during the semiconductor device fabrication process, before transistors and other circuit components are formed. Formation of STI typically involves etching a pattern of trenches in a semiconductor substrate, depositing one or more dielectric materials (e.g., a semiconductor oxide) to fill the trenches, and removing the excess dielectric using a technique such as chemical-mechanical planarization (CMP).
Fabrication tools used for CMP, such as CMP polish pads, often have some elasticity. Accordingly, if there is an STI region with a large area, then the dielectric material existing in the STI trench might be excessively removed near its center. As a result, such portion of the dielectric material might have its height decreased below the height it would have if polishing were ideally planar, an unwanted phenomenon known as “dishing.” The height decrease created in this manner may deform a pattern to be defined in a subsequent lithographic process because a depth of focus may be insufficient.
To prevent the occurrence of dishing, a semiconductor fabrication process may include formation of dummy diffusion within a region of STI. Dummy diffusion may include unetched or deposited semiconductor material of the same semiconductor material making up the semiconductor substrate, but for which no transistor source or drain electrodes are formed. During layout of mask design for the semiconductor manufacturing process, stringent design rules may be applied to ensure an STI region includes a desired level of diffusion density so as to avoid both the electrical current leakage and STI dishing issues described above.
An integrated circuit may include various sized resistors. Larger-sized resistors in an integrated circuit may require more area. Resistors are often formed within integrated circuits using patterns of polycrystalline semiconductor material (e.g., polysilicon). Such resistors are sometime referred to as “polyresistors.” To meet diffusion density design rules when fabricating such resistors, dummy diffusion must often be added within the footprint of the resistors. As shown in FIGS. 1A and 1B, to meet such design rules, a polyresistor may be fabricated on a semiconductor substrate 100 using a plurality of parallel polycrystalline semiconductor resistor arms 102 formed over STI field oxide 104, with dummy diffusion 106 in between resistor arms 102, and metallization 108 perpendicular to resistor arms 102 coupling resistor arms 102 to one another. A drawback to this approach is that dummy diffusion 106 adds significant area to a die layout. Another drawback may be that model accuracy may be compromised if a resistor arm 102 is not a sufficient distance from a neighboring diffusion 106 to ensure that resistor arm 102 is formed on a flat portion of STI 104.